5962-8863401UC 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

生产厂家

5962-8863401UC

5V, Byte Alterable EEPROM

Intersil 

Software Data Protection

VCC

0V

DATA

ADDRESS

AA

5555

CE

WE

X28HC256

55

2AAA

A0

5555

≤tBLC MAX

WRITES

OK

tWC

BYTE

OR

AGE

(VCC)

WRITE

PROTECTED

WRITE DATA AA

TO ADDRESS

5555

WRITE DATA 55

TO ADDRESS

2AAA

WRITE DATA A0

TO ADDRESS

5555

WRITE DATA XX

TO ANY

ADDRESS

WRITE LAST

BYTE TO

LAST ADDRESS

FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE

Regardless of whether the device has previously been

protected or not, once the software data protection algorithm

is used and data has been written, the X28HC256 will

automatically disable further writes unless another command

is issued to cancel it. If no further commands are issued the

X28HC256 will be write protected during power-down and

after any subsequent power-up.

Note: Once initiated, the sequence of write operations

should not be interrupted.

BYTE/PAGE

LOAD ENABLED

OPTIONAL

BYTE/PAGE

LOAD OPERATION

Resetting Software Data Protection

In the event the user wants to deactivate the software data

protection feature for testing or reprogramming in an

EEPROM programmer, the following six step algorithm will

reset the internal protection circuit. After tWC, the X28HC256

will be in standard operating mode.

Note: Once initiated, the sequence of write operations

should not be interrupted.

AFTER tWC

RE-ENTERS DATA

PROTECTED STATE

FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA

PROTECTION

VCC

DATA

AA

55

80

AA

55

20

ADDRESS

5555

2AAA

5555

5555

2AAA

5555

tWC

CE

STANDARD

OPERATING

MODE

WE

FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE

7

FN8108.3

September 21, 2011

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