PACVGA200(2010) 查看數據表（PDF） - ON Semiconductor

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PACVGA200
(Rev.:2010)

VGA Port Companion Circuit

ON Semiconductor 

PACVGA200

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

VON

Voltage drop across level VCC2= 2.5V; VS = GND; IDS = 3mA

shifting NFET when turned

ON

CIN

Input Capacitance

VIDEO_1,VIDEO_2 & VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz

3.0

VIDEO_3 inputs

VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz 3.0

t

SYNC Drivers L => H

PLH

Propagation Delay

C = 50pF; V =5.0V,Input t and t < 5ns

L

CC

R

F

tPHL

SYNC Drivers H => L

Propagation Delay

CL = 50pF; VCC=5.0V; Input tR and tF < 5ns

tR, tF

SYNC Drivers Output Rise CL = 50pF; VCC=5.0V; Input tR and tF < 5ns

5.0

& Fall Times

(measured 10% - 90%)

VESD

ESD Withstand Voltage

VCC1 = VCC3 = VCC4 = 5V; Note 3

±8

0.15

V

4.0

5.0

pF

4.5

5.6

pF

8.0 12.0 ns

8.0 12.0 ns

7.0 10.0 ns

kV

Note 1: All parameters specified over standard operating conditions unless otherwise noted.

Note 2: This parameter applies only to the HSYNC and VSYNC channels. HSYNC and VSYNC have 8mA drivers with RS added

in series to terminate transmission line.

Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC3 and VCC4 must be

bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each

supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with

respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2,

DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body Model

(MIL-STD-883, Method 3015).

Rev. 2 | Page 6 of 10 | www.onsemi.com

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