PACVGA200(2010) 查看數據表（PDF） - ON Semiconductor
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PACVGA200 Datasheet PDF : 10 Pages
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Application Information
PACVGA200
Figure 3. Typical Connection Diagram
A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is
required while the PACVGA200 is in the power-down state. The value of this resistor should be chosen such
that the extra charge deposited into the VCC3 bypass capacitor by each ESD pulse will be discharged before the
next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one
pulse per second. When the PACVGA200 is in the power-up state, an internal discharge resistor is connected
to ground via an FET switch for this purpose.
For the same reason, VCC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there
are no other components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75Ω resistors is not connected internally to GNDD and should ideally be
connected to the ground of the video DAC IC.
Rev. 2 | Page 8 of 10 | www.onsemi.com
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