74AHCT157-Q100 查看數據表（PDF） - NXP Semiconductors.
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74AHCT157-Q100 Datasheet PDF : 17 Pages
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74AHC157-Q100;
74AHCT157-Q100
Quad 2-input multiplexer
Rev. 1 — 4 July 2013
Product data sheet
1. General description
The 74AHC157-Q100; 74AHCT157-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74AHC157-Q100; 74AHCT157-Q100 is a quad 2-input multiplexer which selects 4
bits of data from two sources under the control of a common data select input (S). The
enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced
LOW regardless of all other input conditions. Moving the data from two groups of registers
to four common output buses is a common use of the 74AHC157-Q100;
74AHCT157-Q100. The state of the common data select input (S) determines the
particular register from which the data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common. The 74AHC157-Q100;
74AHCT157-Q100 is logic implementation of a 4-pole, 2-position switch. The logic levels
applied to S, determines the position of the switch.
The logic equations are:
1Y = E (1I1 S + 1I0 S)
2Y = E (2I1 S + 2I0 S)
3Y = E (3I1 S + 3I0 S)
4Y = E (4I1 S + 4I0 S)
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Input levels:
For 74AHC157-Q100: CMOS level
For 74AHCT157-Q100: TTL level
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