74HCT109PW,112 查看數據表（PDF） - NXP Semiconductors.

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74HCT109PW,112

Dual JK flip-flop with set and reset; positive-edge-trigger

NXP Semiconductors. 

Nexperia

74HC109; 74HCT109

Dual JK flip-flop with set and reset; positive-edge-trigger

6. Functional description

Table 3. Function selection[1]

Operating modes

Input

Output

nSD

nRD

nCP

nJ

nK

nQ

nQ

Asynchronous set

L

H

X

X

X

H

L

Asynchronous reset

H

L

X

X

X

L

H

Undetermined

L

L

X

X

X

H

H

Toggle

H

H



h

l

q

q

Load 0 (reset)

H

H



l

l

L

H

Load 1 (set)

H

H



h

h

H

L

Hold no change

H

H



l

h

q

q

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition

L = LOW voltage level

l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition

q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition

X = don’t care

 = LOW-to-HIGH CP transition

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max Unit

VCC

IIK

IOK

IO

ICC

IGND

Tstg

Ptot

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

VI < 0.5 V or VI > VCC + 0.5 V

VO < 0.5 V or VO > VCC + 0.5 V

0.5 V < VO < VCC + 0.5 V

SO16 and (T)SSOP16 packages

0.5

-

-

-

-

50

65

[1]

-

+7 V

20 mA

20 mA

25 mA

+50 mA

-

mA

+150 C

500 mW

[1] For SO16 packages: above 70 C, the value of Ptot derates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60 C, the value of Ptot derates linearly with 5.5 mW/K.

74HC_HCT109

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 1 August 2016

© Nexperia B.V. 2017. All rights reserved

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