74HCT109D,652 查看數據表（PDF） - NXP Semiconductors.
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74HCT109D,652 Datasheet PDF : 19 Pages
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Nexperia
74HC109; 74HCT109
Dual JK flip-flop with set and reset; positive-edge-trigger
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min
Max
Min
Max
tW
pulse width nCP HIGH or LOW;
see Figure 6
VCC = 2.0 V
80 19 -
100
-
120
VCC = 4.5 V
16 7
-
20
-
24
VCC = 6.0 V
14 6
-
17
-
20
nSD, nRD HIGH or LOW;
see Figure 7
-
ns
-
ns
-
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
trec
recovery time nSD, nRD to nCP;
see Figure 7
80 14 -
100
-
120
16 5
-
20
-
24
14 4
-
17
-
20
-
ns
-
ns
-
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tsu
set-up time nJ and nK to nCP;
see Figure 6
70 19 -
90
14 7
-
18
12 6
-
15
-
105
-
21
-
18
-
ns
-
ns
-
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
th
hold time
nJ and nK to nCP;
see Figure 6
70 17 -
90
14 6
-
18
12 5
-
15
-
105
-
21
-
18
-
ns
-
ns
-
ns
VCC = 2.0 V
5
0
-
5
-
5
VCC = 4.5 V
5
0
-
5
-
5
VCC = 6.0 V
5
0
-
5
-
5
fmax
maximum
nCP; see Figure 6
frequency
VCC = 2.0 V
6 22 -
5
-
4
VCC = 4.5 V
30 68 -
24
-
20
VCC = 5 V; CL = 15 pF
- 75 -
-
-
-
VCC = 6.0 V
35 81 -
28
-
24
CPD
power
CL = 50 pF; f = 1 MHz; [4] -
20
-
-
-
-
dissipation VI = GND to VCC
capacitance
-
ns
-
ns
-
ns
-
MHz
-
MHz
-
MHz
-
MHz
-
pF
74HC_HCT109
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 August 2016
© Nexperia B.V. 2017. All rights reserved
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