74LVC109D 查看數據表（PDF） - NXP Semiconductors.

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74LVC109D

Dual JK flip-flop with set and reset; positive-edge trigger

NXP Semiconductors. 

Philips Semiconductors

Dual JK flip-flop with set and reset;

positive-edge trigger

Product specification

74LVC109

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

VCC

supply voltage

VI

VO

Tamb

tr, tf

input voltage

output voltage

ambient temperature

input rise and fall times

CONDITIONS

MIN.

for maximum speed performance 2.7

for low-voltage applications

1.2

0

0

in free air

−40

VCC = 1.2 to 2.7 V

0

VCC = 2.7 to 3.6 V

0

MAX.

3.6

3.6

5.5

VCC

+125

20

10

UNIT

V

V

V

V

°C

ns/V

ns/V

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

SYMBOL

VCC

IIK

VI

IOK

VO

IO

ICC, IGND

Tstg

Ptot

PARAMETER

supply voltage

input diode current

input voltage

output diode current

output voltage

output source or sink current

VCC or GND current

storage temperature

power dissipation

CONDITIONS

VI < 0

note 1

VO > VCC or VO < 0

note 1

VO = 0 to VCC

Tamb = −40 to +125 °C; note 2

MIN.

−0.5

−

−0.5

−

−0.5

−

−

−65

−

MAX.

UNIT

+6.5

V

−50

mA

+6.5

V

±50

mA

VCC + 0.5 V

±50

mA

±100

mA

+150

°C

500

mW

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

2004 Mar 18

6

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