74VHC08BQ-Q100 查看數據表（PDF） - NXP Semiconductors.

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74VHC08BQ-Q100

Quad 2-input AND gate

NXP Semiconductors. 

Nexperia

74VHC08-Q100; 74VHCT08-Q100

Quad 2-input AND gate

5. Pinning information

5.1 Pinning

9+&4

9+&74

$ 

% 

< 

$ 

% 

< 

*1' 

 9&&

 %

 $

 <

 %

 $

 <

DDD

Fig 4. Pin configuration SO14 and TSSOP14

9+&4

9+&74

WHUPLQDO

LQGH[DUHD

% 

< 

$ 

% 

< 

*1'

 %

 $

 <

 %

 $

DDD

7UDQVSDUHQWWRSYLHZ

(1) The die substrate is attached to this pad using

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 5. Pin configuration DHVQFN14

5.2 Pin description

Table 2.

Symbol

1A

1B

1Y

2A

2B

2Y

GND

3Y

3A

3B

4Y

4A

4B

VCC

Pin description

Pin

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Description

data input

data input

data output

data input

data input

data output

ground (0 V)

data output

data input

data input

data output

data input

data input

supply voltage

74VHC_VHCT08_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 20 December 2013

© Nexperia B.V. 2017. All rights reserved

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