LFSCM3GA25E-5FC1704I 查看數據表（PDF） - Lattice Semiconductor

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LFSCM3GA25E-5FC1704I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Figure 2-1. Simplified Block Diagram (Top Level)

Quad SERDES

sysCLOCK

Analog PLLs

sysCLOCK DLLs

Programmable

I/O Cell (PIC) includes

PURESPEED I/O Interface

Each PIC

contains four

Programmable

I/Os (PIO)

Three PICs

per four PFUs

sysCLOCK

Analog PLLs

Architecture

LatticeSC/M Family Data Sheet

Quad SERDES

Physical Coding

Sublayer (PCS)

Structured ASIC

Block (MACO)

Programmable

Function

Unit (PFU)

sysMEM Embedded

Block RAM (EBR)

sysCLOCK DLLs

2-2

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