LFSC3GA80E-6FC1704I 查看數據表（PDF） - Lattice Semiconductor

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LFSC3GA80E-6FC1704I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Figure 2-3. Slice Diagram

A1

B1

C1

D1

From

Routing

M1

M0

A0

B0

C0

D0

Architecture

LatticeSC/M Family Data Sheet

FCO from Slice/PFU,

FCI into Different Slice/PFU

CO

F

LUT4 &

CARRY

CI

Slice

D

FF/

Latch

CO

LUT4 & F

CARRY

CI

LUT

Expansion

Mux

OFX0

D

FF/

Latch

OFX1

F1

Q1

OFX0

To

Routing

F0

Q0

Control Signals CE

selected and

CLK

inverted per

slice in routing

LSR

Note: some interslice

signals not shown.

FCI into Slice/PFU,

FCO from Different Slice/PFU

Table 2-1. Slice Signal Descriptions

Function

Type

Signal Names

Description

Input

Data signal

A0, B0, C0, D0 Inputs to LUT4

Input

Data signal

A1, B1, C1, D1 Inputs to LUT4

Input

Multi-purpose

M0

Multipurpose Input

Input

Multi-purpose

M1

Multipurpose Input

Input

Control signal

CE

Clock Enable

Input

Control signal

LSR

Local Set/Reset

Input

Control signal

CLK

System Clock

Input

Inter-PFU signal

FCI

Fast Carry In1

Output

Data signals

F0, F1

LUT4 output register bypass signals

Output

Data signals

Q0, Q1

Register Outputs

Output

Data signals

OFX0

Output of a LUT5 MUX

Output

Data signals

OFX1

Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output

Inter-PFU signal

FCO

For the right most PFU the fast carry chain output2

1. See Figure 2-2 for connection details.

2. Requires two PFUs.

2-4

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