AD5341(Rev0) 查看數據表（PDF） - Analog Devices
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AD5341
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD5341 Datasheet PDF : 20 Pages
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AD5330/AD5331/AD5340/AD5341
AC CHARACTERISTICS1 (VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX
unless otherwise noted.)
Parameter2
B Version3
Min Typ Max
Unit Conditions/Comments
Output Voltage Settling Time
AD5330
AD5331
AD5340
AD5341
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
6
8
7
9
8
10
8
10
0.7
6
0.5
200
–70
NOTES
1Guaranteed by design and characterization, not production tested.
2See Terminology section.
3Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
Specifications subject to change without notice.
VREF = 2 V. See Figure 20
µs
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
µs
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
µs
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
µs
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
V/µs
nV-s 1 LSB Change Around Major Carry
nV-s
kHz
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
dB
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
TIMING CHARACTERISTICS1, 2, 3
(VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.)
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Limit at TMIN, TMAX
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Condition/Comments
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode. WR Falling to LDAC Falling.
Synchronous Mode. LDAC Falling to WR Rising.
Synchronous Mode. WR Rising to LDAC Rising.
Asynchronous Mode. LDAC Rising to WR Rising.
Asynchronous Mode. WR Rising to LDAC Falling.
LDAC Pulsewidth
CLR Pulsewidth
Time Between WR Cycles
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2.
3See Figure 1.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC1
LDAC2
t1
t2
t3
t 13
t4
t5
t6
t7
t8
t9
t 10
t 11
t 12
CLR
NOTES:
1 SYNCHRONOUS LDAC UPDATE MODE
2 ASYNCHRONOUS LDAC UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
REV. 0
–3–
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