AD5629R 查看數據表（PDF） - Analog Devices
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AD5629R Datasheet PDF : 30 Pages
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Data Sheet
AD5629R/AD5669R
I2C TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted.
Table 4.
Parameter Conditions
Min
fSCL1
Standard mode
Fast mode
t1
Standard mode 4
Fast mode
0.6
t2
Standard mode 4.7
Fast mode
1.3
t3
Standard mode 250
Fast mode
100
t4
Standard mode 0
Fast mode
0
t5
Standard mode 4.7
Fast mode
0.6
t6
Standard mode 4
Fast mode
0.6
t7
Standard mode 4.7
Fast mode
1.3
t8
Standard mode 4
Fast mode
0.6
t9
Standard mode
Fast mode
t10
Standard mode
Fast mode
t11
Standard mode
Fast mode
t11A
Standard mode
Fast mode
t12
Standard mode
Fast mode
t13
Standard mode 10
Fast mode
10
t14
Standard mode 300
Fast mode
300
t15
Standard mode 20
Fast mode
20
tSP2
Fast mode
0
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus-free time between a stop and a start condition
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
tFCL, fall time of SCL signal
LDAC pulse width low
Falling edge of ninth SCL clock pulse of last byte of a valid write to
the LDAC falling edge
CLR pulse width low
Pulse width of spike suppressed
1 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
Rev. F | Page 7 of 30
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