AD5694ARUZ 查看數據表（PDF） - Analog Devices
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AD5694ARUZ Datasheet PDF : 24 Pages
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AD5696/AD5694
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2 Min
Max
Unit
Description
t1
2.5
μs
SCL cycle time
t2
0.6
μs
tHIGH, SCL high time
t3
1.3
μs
tLOW, SCL low time
t4
0.6
μs
tHD,STA, start/repeated start hold time
t5
100
t63
0
ns
0.9
μs
tSU,DAT, data setup time
tHD,DAT, data hold time
t7
0.6
μs
tSU,STA, repeated start setup time
t8
0.6
μs
tSU,STO, stop condition setup time
t9
1.3
μs
tBUF, bus free time between a stop condition and a start condition
t104
0
300
ns
tR, rise time of SCL and SDA when receiving
t114, 5
20 + 0.1CB
300
ns
tF, fall time of SCL and SDA when transmitting/receiving
t12
20
ns
LDAC pulse width
t13
400
ns
SCL rising edge to LDAC rising edge
tSP6
0
CB5
50
ns
400
pF
Pulse width of suppressed spike
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL
falling edge.
4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD.
5 CB is the total capacitance of one bus line in pF.
6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Timing Diagram
START
CONDITION
SDA
SCL
t9
t10
t3
t4
t6
LDAC1
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
REPEATED START
CONDITION
t11
t4
t2
t5
t1
t7
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8
t12
Rev. A | Page 6 of 24
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