AD7452_15 查看數據表（PDF） - Analog Devices
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AD7452_15 Datasheet PDF : 24 Pages
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AD7452
DIGITAL INPUTS
The digital inputs applied to the AD7452 are not limited by the
maximum ratings, which limit the analog limits. Instead the
digital inputs applied, that is, CS and SCLK, can go to 7 V and
are not restricted by the VDD + 0.3 V limits as on the analog
input.
The main advantage of the inputs being unrestricted to the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS and SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V was applied prior to VDD.
REFERENCE
An external reference source is required to supply the reference
to the AD7452. This reference input can range from 100 mV to
3.5 V. With a 5 V power supply, the specified reference is 2.5 V
and the maximum reference is 3.5 V. With a 3 V power supply,
the specified reference is 2 V and the maximum reference is
2.2 V. In both cases, the reference is functional from 100 mV.
It is important to ensure that when choosing the reference value
for a particular application, the maximum analog input range
(VIN max) is never greater than VDD + 0.3 V to comply with the
maximum ratings of the device. The following two examples
calculate the maximum VREF input that can be used when
operating the AD7452 at a VDD of 5 V and 3 V, respectively.
Example 1
VIN max = VDD + 0.3
VIN max = VREF + VREF/2
If VDD = 5 V, then VIN max = 5.3 V.
Therefore
3 × VREF/2 = 5.3 V
VREF max = 3.5 V
Thus, when operating at VDD = 5 V, the value of VREF can range
from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V,
VREF max = 3.17 V.
Example 2
VIN max = VDD + 0.3
VIN max = VREF + VREF/2
If VDD = 3 V, then VIN max = 3.3 V.
Therefore
3 × VREF/2 = 3.3 V
VREF max = 2.2 V
Thus, when operating at VDD = 3 V, the value of VREF can range
from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V,
VREF max = 2 V.
Data Sheet
These examples show that the maximum reference applied to
the AD7452 is directly dependent on the value applied to VDD.
The value of the reference sets the analog input span and the
common-mode voltage range. Errors in the reference source
result in gain errors in the AD7452 transfer function and add to
specified full-scale errors on the part. A 0.1 µF capacitor should
be used to decouple the VREF pin to GND.
Figure 33 shows a typical connection diagram for the VREF pin.
VDD
VDD
0.1µF
10nF
AD780
NC
0.1µF
1
OPSEL 8 NC
2 VIN
7 NC
3 TEMP VOUT 6 2.5V
4 GND TRIM 5 NC
AD7452*
VREF
0.1µF
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Typical VREF Connection Diagram for VDD = 5 V
Table 5. Examples of Suitable Voltage References
Output
Initial
Operating
Reference Voltage (V) Accuracy (%) Current (µA)
AD780
2.5/3
0.04
1000
ADR421
2.5
0.04
500
ADR420
2.048
0.05
500
SINGLE-ENDED OPERATION
When supplied with a 5 V power supply, the AD7452 can han-
dle a single-ended input. The design of this part is optimized for
differential operation, so with a single-ended input, perfor-
mance degrades. Linearity degrades by 0.2 LSB typically, the
full-scale errors degrade by 1 LSB typically, and ac performance
is not guaranteed.
To operate the AD7452 in single-ended mode, the VIN+ input is
coupled to the signal source, while the VIN– input is biased to
the appropriate voltage corresponding to the midscale code
transition. This voltage is the common mode, which is a fixed
dc voltage (usually the reference). The VIN+ input swings around
this value and should have a voltage span of 2 × VREF to make
use of the full dynamic range of the part. The input signal
therefore has peak-to-peak values of common mode ± VREF. If
the analog input is unipolar, an op amp in a noninverting unity
gain configuration can be used to drive the VIN+ pin. Because
the ADC operates from a single supply, it is necessary to level
shift ground-based bipolar signals to comply with the input
requirements. An op amp can be configured to rescale and level
shift the ground-based bipolar signal so it is compatible with
the selected input range of the AD7452 (see Figure 34).
Rev. C | Page 18 of 24
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