AD7452_15 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD7452_15 Datasheet PDF : 24 Pages
| |||
Data Sheet
AD7452
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V;
VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCLK2
tCONVERT
tQUIET
t1
t2
t33
t43
t5
t6
t7
t84
tPOWER-UP5
Limit at TMIN, TMAX
10
10
16 × tSCLK
1.6
60
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
Unit
kHz min
MHz max
μs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
Description
tSCLK = 1/fSCLK
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
1 Common-mode voltage.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, or 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power-Up Time section.
CS
t2
SCLK
t3
SDATA
t1
t5
tCONVERT
B
1
2
3
4
5
13
14
t4
t7
t6
0
0
0
0
DB11
DB10
DB2
DB1
4 LEADING ZEROS
Figure 2. Serial Interface Timing Diagram
15
t8
DB0
16
tQUIET
THREE-STATE
Rev. C | Page 5 of 24
Share Link: 