AD7452 查看數據表（PDF） - Analog Devices

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AD7452

ANALOG TO DIGITAL CONVERTER ADC, 12 BIT, 555KSPS, SOT-23-8

Analog Devices 

Data Sheet

AD7452

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD 1

8 VREF

SCLK 2 AD7452 7 VIN+

SDATA 3 TOP VIEW 6 VIN–

(Not to Scale)

CS 4

5 GND

Figure 4. 8-Lead SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Mnemonic Function

VREF

Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is

2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin

should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details.

VIN+

Positive Terminal for Differential Analog Input.

VIN–

Negative Terminal for Differential Analog Input.

GND

Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference

signal should be referred to this GND voltage.

CS

Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing

the serial data transfer.

SDATA

Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits

are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of

conversion data, which are provided MSB first. The output coding is twos complement.

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the

clock source for the conversion process.

VDD

Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor

and a 10 µF tantalum capacitor in parallel.

Rev. C | Page 7 of 24

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