µPD16431A
CONFIGURATION OF KEY DATA LATCH
The key data is latched as illustrated below and is read by a read command, starting from the most
significant bit. Key data is read once a frame and latched when coinciding with the immediadtely preceding
data. In other words, it requires at least 2 frames from the time the key is pressed till data is confirmed to
be the key data (the key request becoming H).
32-bit latch/SHIFT register
MSB
LSB
KS8
KS7
KS6
KS5
KS4
KS3
KS2
KS1
The key data is 0 when off and 1 when on.
KEY INPUT EQUIVALENT CIRCUIT
KEY4 KEY3 KEY2 KEY1
To key latch
KEY n
Pull-down
control signal
• The pull-down control signal goes high only during key
source output and turns on the pull-down transistor.
• The on-resistance of the pull-down transistor is several kΩ.
8