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AS1720 查看數據表(PDF) - austriamicrosystems AG

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AS1720 Datasheet PDF : 12 Pages
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AS1720
Datasheet - Detailed Description
8 Detailed Description
Delay
The delay time is generated internally by a digital divider.
LDO and Reference Generator
This block provides the internal supply voltage of typ. 3.3V and all bias currents for the analog cells. Further the external resistor divider for
setting the duty cycle will be supplied.
Thermal shutdown
The temperature is constantly monitored. If the temperature exceeds typ. 160ºC the output is disabled. In order to exit the over temperature
condition, the device has to cool down and the reason of over temperature (e.g. short circuit) must be removed. After exiting the overtemperature
condition the system restarts beginning with the energizing phase followed by the hold phase.
DC Operation (AS1720A only)
After power up, the delay time (see Delay) starts running. After expiration of the delay the hold phase starts automatically. During the hold phase
the DC output current is reduced according to the RIH on pin IH.
PWM Operation (AS1720B only)
After power up, the delay time (see Delay) starts running. After expiration of the delay the hold phase starts automatically. The internal RC
oscillator sets the PWM period. The duty cycle is either defined by the external resistor divider (voltage) at pin DUTY or by the fixed internal
divider. When using the external divider the duty cycle can be adjusted between 20% and 90% (e.g. from a DAC). Alternatively the pin can be
driven by a voltage source. For using the internal divider the pin DUTY has to be connected to VDDA. The comparator recognizes this condition
and switches to the internal divider, which causes a fixed 50% duty cycle.
DUTYCYCLE(VDUTY) = 0, 381 × VDUTY – 0, 014
(EQ 1)
Figure 9. Simplified Circuit of Block PWM and Control
VDDA
R1
adjustable
Duty cycle
DUTY
R2
Vref
optional
fixed
VDDA
50% Duty cycle
DUTY
Internal VDDA typ. 3.3V
30kHz
Oscillator
Delay
PWM &
Control
VDDA
RPU
ENN
Off
On
www.austriamicrosystems.com/Solenoid-Relay-Driver/AS1720 Revision 1.04
6 - 12

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