ISPXPLD5512MX 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Macrocell

The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each

macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks

and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP.

Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output

capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function

for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O

cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be

clocked from one of several global or product term clocks available on the device. A global and product term clock

enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset

for the macrocell register is provided from both global and product term signals. The macrocell register can be pro-

grammed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell.

Figure 8. Macrocell

From

I/O Cell

PTSA Bypass

Output to

I/O Block

From PTSA

DQ

PT Clock

Shared

PT CE

Clk En

Shared PT Clock

CLK0

CLK1

CLK2

CLK3

PT Preset

PT Reset

Shared PT Reset

Global Reset

R/L

Clk

PR

GRP

Memory Modes

The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in

Table 4. The remainder of this section details operation of each of the memory modes. Additional information

regarding the memory modes can also be found in technical note number TN1030, Using Memory in ispXPLD

5000MX Devices.

8

Share Link: