74LVC32A(2018) 查看數據表（PDF） - NXP Semiconductors.
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74LVC32A Datasheet PDF : 14 Pages
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Nexperia
74LVC32A
Quad 2-input OR gate
10.1. Waveforms and test circuit
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
nA, nB input
GND
VM
t PHL
t PLH
VCC
VI
PULSE
GENERATOR
VO
DUT
RT
CL
RL
nY output
VM
Fig. 7.
mna244
VM = 1.5 V at VCC ≥ 2.7 V
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that
occur with the output load.
The input nA, nB to output nY propagation
delays
Fig. 8.
001aaf615
Test data is given in Table 8.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe
capacitance.
RT = Termination resistance should be equal to
output impedance Zo of the pulse generator.
Test circuit for measuring switching times
Table 8. Test data
Supply voltage
1.2 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Input
VI
VCC
VCC
VCC
2.7 V
2.7 V
tr, tf
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
Load
CL
30 pF
30 pF
30 pF
50 pF
50 pF
RL
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
74LVC32A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 12 September 2018
© Nexperia B.V. 2018. All rights reserved
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