FSL4110LR 查看數據表（PDF） - Fairchild Semiconductor

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FSL4110LR

Green Mode Fairchild Power Switch

Fairchild Semiconductor 

Pin Configuration

GND 1

VCC 2

FB 3

VIN 4

7 Drain

6 Drain

5 VSTR

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin #

1

2

3

4

5

6, 7

Name

GND

VCC

FB

VIN

VSTR

Drain

Description

Ground. The SenseFET source terminal on primary side and the internal PWM control ground.

Power Supply Voltage Input. This pin is the positive supply input, which provides the internal

operating current for startup and steady-state operation. This voltage is supplied from internal

high-voltage regulator via pin 5 (VSTR) during startup (see Figure 2). When the external bias

voltage is higher than 10 V, internal high voltage regulator is disable. A ceramic capacitor need

to be placed as close as possible between this pin and pin 1 (GND). Recommended distance is

less than 3 mm.

Feedback. This pin is internally connected to the inverting input to the PWM comparator. This

pin has a 100 μA current source internally. The collector of an opto-coupler is typically tied to

this pin. A capacitor should be placed between this pin and GND. A resitor should be

connected between this pin and pin 2 (VCC) to generate delay current (IDELAY) for overload

protection delay time. The resistance should not be exceed 5 M in self-biasing.

Line Over-Voltage Input. This pin is the input of divided line voltage. The voltage is devided by

resistors. When this voltage is higher than 2 V, the FSL4110LR is not operationed. If this pin is

not used, it should be connected to the ground.

Startup. Connected to the rectified AC line voltage source. At startup, the internal switch

supplies internal bias and charges an external storage capacitor placed between VCC pin and

ground. Once VCC reaches 12 V, all internal blocks are activated. The internal high-voltage

regulator turns on and off to maintain VCC at 10 V without auxiliary bias winding.

Drain. Designed to connect directly to the primary lead of the transformer and capable of

switching a maximum of 1000 V. Minimizing the length of the trace connecting these pins to the

transformer decreases leakage inductance.

© 2014 Fairchild Semiconductor Corporation

FSL4110LR • Rev. 1.3

3

www.fairchildsemi.com

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