7005S17PFB8 查看數據表（PDF） - Integrated Device Technology

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7005S17PFB8

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA

tOH

A0-A2

VALID ADDRESS

VALID ADDRESS

SEM

tAW

tWR

tEW

tACE

DATA0

R/W

tDW

tSOP

DATAIN VALID

tAS

tWP

tDH

DATA OUT

VALID

tSWRD

OE

Write Cycle

NOTE:

1. CE = VIH for the duration of the above timing (both write and read cycle).

tSOP

Read Cycle

tAOE

2738 drw 11

Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A"

MATCH

SIDE(2) “A”

R/W"A"

SEM"A"

A0"B"-A2"B"

tSPS

MATCH

SIDE(2) “B”

R/W"B"

SEM"B"

2738 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.

3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

61.412

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