7005S17J8 查看數據表（PDF） - Integrated Device Technology
零件编号
产品描述 (功能)
生产厂家
7005S17J8 Datasheet PDF : 21 Pages
| |||
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
IDT7005S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 20/35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
◆ Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆ IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
◆ M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Devices are capable of withstanding greater than 2001V
electrostatic discharge
◆ Battery backup operation—2V data retention
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 68-pin PGA, PLCC and a 64-pin thin quad
flatpack
◆ Industrial temperature range (-40°C to +85°C) is available for
selected speeds
◆ Green parts available, see ordering information
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A12L
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2018 Integrated Device Technology, Inc.
I/O0R-I/O7R
BUSYR(1,2)
A12R
A0R
SEMR
INTR(2)
2738 drw 01
MARCH 2018
DSC 2738/19
Share Link: 