LH28F016LL 查看數據表（PDF） - Sharp Electronics

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LH28F016LL

16M (1M × 16, 2M × 8) Flash Memory

Sharp Electronics 

16M (1M × 16, 2M × 8) Flash Memory

LH28F016LL

INTRODUCTION

Sharp’s LH28F016LL 16M Flash Memory is a revo-

lutionary architecture which enables the design of truly

mobile, high performance, personal computing and com-

munication products. With innovative capabilities,

3 V single voltage operation and very high read/write

performance, the LH28F0166LL is also the ideal choice

for designing embedded mass storage flash memory

systems.

The LH28F016LL is very high density, highest per-

formance non-volatile read/write solution for solid-state

storage applications. Its symmetrically blocked archi-

tecture (100% compatible with the LH28F016SU 16M

Flash memory), extended cycling, minimum power

2.7 V operation, very fast write and read performance

and selective block locking provide a highly flexible

memory component suitable for battery operation por-

table equipment such as digital still camera, PDA, cel-

lular phone, and memory card. Its x8/x16 architecture

allows the optimization of memory to processor inter-

face. The flexible block locking option enables bundling

of executable of executable application software in a

Resident Flash Array or memory card. Manufactured

on Sharp’s 0.6 µm ETOX™ process technology, the

LH28F016LL is the most cost-effective, high-density

3 V single power operation flash memory.

DESCRIPTION

The LH28F016LL is a high performance 16M

(16,777,216 bit) block erasable non-volatile random

access memory organized as either 1M × 16 or 2M x 8.

The LH28F016LL includes thirty-two 64K (65,536)

blocks or thirty-two 32-KW (32,768) blocks. A chip

memory map is shown in Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F016LL:

• 3 V Write/Erase Operation (3 V VPP)

• 3 V Low Power Capability

• Improved Write Performance

• Dedicated Block Write/Erase Protection

The LH28F016LL will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-

age.This form factor and pinout allow for very high board

layout densities.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or

microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word

Writes and Block Erase operations to be executed us-

ing a Two-Write command sequence to the CUI in the

same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher

write performance and provide additional capabilities.

These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or

word increments typically within 9 µs, a 15% improve-

ment over the LH28F008SA.

Each block can be written and erased a minimum of

100,000 cycles. Systems can achieve 1,000,000 Block

Erase Cycles by providing wear-leveling algorithms and

graceful block retirement. These techniques have

already been employed in many flash file systems and

Hard Disk Drive designs.

The LH28F016LL incorporates two Page Buffers of

256 Bytes (128 Words) each to allow page data writes.

This feature can improve a system write performance

by up to 4.8 times over previous flash memory devices.

All operations are started by a sequence of Write

commands to the device. Three Status Registers (de-

scribed in detail later) and a RY »/BY » output pin provide

information on the progress of the requested operation.

While the LH28F008SA requires an operation to com-

plete before the next operation can be requested, the

LH28F016LL allows queuing of the next operation while

the memory executes the current operation. This elimi-

nates system overhead when writing several bytes in a

row to the array or erasing several blocks at the same

time. The LH28F016LL can also perform write opera-

tions to one block of memory while performing erase of

another block.

The LH28F016LL provides user-selectable block

locking to protect code or data such as Device Drivers,

PCMCIA card information, ROM-Executable O/S or

Application Code. Each block has an associated non-

volatile lock-bit which determines the lock status of the

block. In addition, the LH28F016LL has a master Write

Protect pin (WP ») which prevents any modifications to

memory blocks whose lock-bits are set.

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