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LH28F016SU 查看數據表(PDF) - Sharp Electronics

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LH28F016SU
Sharp
Sharp Electronics Sharp
LH28F016SU Datasheet PDF : 37 Pages
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LH28F016SU
16M (1M × 16, 2M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
WP 56
WE 55
OE 54
RY/BY 53
DQ15 52
DQ7 51
DQ14 50
DQ6 49
GND 48
DQ13 47
DQ5 46
DQ12 45
DQ4 44
VCC 43
GND 42
DQ11 41
DQ3 40
DQ10 39
DQ2 38
VCC 37
DQ9 36
DQ1 35
DQ8 34
DQ0 33
A0 32
BYTE 31
NC 30
NC 29
1 3/5
2 CE1
3 NC
4 A20
5 A19
6 A18
7 A17
8 A16
9 VCC
10 A15
11 A14
12 A13
13 A12
14 CE0
15 VPP
16 RP
17 A11
18 A10
19 A9
20 A8
21 GND
22 A7
23 A6
24 A5
25 A4
26 A3
27 A2
28 A1
28F016SUT-17
Figure 2. TSOP Reverse Bend Configuration
INTRODUCTION
Sharp’s LH28F016SU 16M Flash Memory is a revo-
lutionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities, 5 V
single voltage operation and very high read/write per-
formance, the LH28F016SU is also the ideal choice for
designing embedded mass storage memory systems.
The LH28F016SU is a very high density, highest per-
formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F008SA 8M
Flash memory), extended cycling, low power 3.3 V
operation, very fast write and read performance and
selective block locking provide a highly flexible memory
component suitable for high density memory cards,
Resident Flash Arrays and PCMCIA-ATA Flash Drives.
The LH28F016SU’s dual read voltage enables the
design of memory cards which can interchangeably be
read/written in 3.3 V and 5.0 V systems. Its x8/x16
architecture allows the optimization of memory to pro-
cessor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp’s 0.55 µm ETOX™ process technology, the
LH28F016SU is the most cost-effective, high-density
3.3 V flash memory.
DESCRIPTION
The LH28F016SU is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M × 8.
The LH28F016SU includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 4.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F016SU:
5 V Write/Erase Operation (5 V VPP)
3.3 V Low Power Capability (2.7 V VCC Read)
Improved Write Performance
Dedicated Block Write/Erase Protection
A 3/5 » input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
The LH28F016SU will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-
age.This form factor and pinout allow for very high board
layout densities.
2

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