HEF4046B(2016) 查看數據表（PDF） - NXP Semiconductors.

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HEF4046B
(Rev.:2016)

Phase-locked loop

NXP Semiconductors. 

Nexperia

HEF4046B

Phase-locked loop

11.1 VCO component selection

Recommended range for R1 and R2: 10 k to 1 M; for C1: 50 pF to any practical value.

1. VCO without frequency offset (R2 = ). 

a. Given f0: use f0 with Figure 7 to determine R1 and C1.

b. Given fmax: calculate f0 from f0 = 0.5fmax; use f0 with Figure 7 to determine R1 and

C1.

2. VCO with frequency offset.

a. Given f0 and 2fL : calculate fmin from the equation fmin = f0  2fL; use fmin with

Figure 8 to determine R2 and C1; calculate f--m----a---x from the equation

fmin

f--m----a---x = f--0----+-----2---f--L- ; use f--m----a---x with Figure 9 to determine the ratio R2/R1 to obtain

fmin f0 – 2fL

fmin

R1.

b. Given fmin and fmax: use fmin with Figure 8 to determine R2 and C1; calculate

f--m----a---x ;

fmin

use f--m----a---x with Figure 9 to determine R2/R1 to obtain R1.

fmin



IR

+]



DDH



































     

&S)

Fig 7.

Tamb = 25 C; VCO_IN at 0.5VDD;

INH_IN at VSS; R2 = .

Lines (1), (4), and (7): VDD = 15 V;

Lines (2), (5), and (8): VDD = 10 V;

Lines (3), (6), and (9): VDD = 5 V;

Lines (1), (2), and (3): R1 = 10 k;

Lines (4), (5), and (6): R1 = 100 k;

Lines (7), (8), and (9): R1 = 1 M.

Typical center frequency as a function of

capacitor C1



IPLQ

+]













DDH

























     

&S)

Tamb = 25 C; VCO_IN at VSS; INH_IN at VSS; R1 = .

Lines (1), (4), and (7): VDD = 15 V;

Lines (2), (5), and (8): VDD = 10 V;

Lines (3), (6), and (9): VDD = 5 V;

Lines (1), (2), and (3): R2 = 10 k;

Lines (4), (5), and (6): R2 = 100 k;

Lines (7), (8), and (9): R2 = 1 M.

Fig 8. Typical frequency offset as a function of

capacitor C1

HEF4046B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 24 March 2016

© Nexperia B.V. 2017. All rights reserved

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