CY7C1381D-133AXI(2011) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1381D-133AXI Datasheet PDF : 34 Pages
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Definitions (continued)
Name
DQs
DQPX
MODE
VDD
VDDQ
VSS
VSSQ
TDO
TDI
TMS
TCK
NC
VSS/DNU
I/O
Description
I/O
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are
automatically tristated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state
of OE.
I/O
Synchronous
Input Static
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During
write sequences, DQPX is controlled by BWX correspondingly.
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull-up.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous feature is not being used, this pin can be left unconnected. This pin is not available on TQFP
packages.
JTAG Serial Input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being used, this pin can be left floating or connected to VDD through a pull-up resistor.
This pin is not available on TQFP packages.
JTAG Serial Input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being used, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
JTAG
Clock
–
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
Ground/DNU This pin can be connected to ground or can be left floating.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F supports
secondary cache in systems using a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with the processor address strobe
(ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Document Number: 38-05544 Rev. *I
Page 9 of 34
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