74LVC06A 查看數據表（PDF） - NXP Semiconductors.
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74LVC06A Datasheet PDF : 14 Pages
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NXP Semiconductors
4. Functional diagram
74LVC06A
Hex inverter with open-drain outputs
1 1A
1Y 2
3 2A
2Y 4
5 3A
3Y 6
9 4A
4Y 8
11 5A
5Y 10
13 6A
6Y 12
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Fig 1. Logic symbol
1
1A
1
2 1Y
3
2A
1
4 2Y
5
3A
1
6 3Y
9
4A
1
8
4Y
11
1
5A
10
5Y
13
1
6A
12
6Y
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Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
Y
A
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GND
Fig 3. Logic diagram for one gate
74LVC06A
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
14 VCC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
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Fig 4. Pin configuration for SO14 and TSSOP14
74LVC06A
terminal 1
index area
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND(1)
13 6A
12 6Y
11 5A
10 5Y
9 4A
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Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN14
74LVC06A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 10 November 2011
© NXP B.V. 2011. All rights reserved.
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