MAX4760(2007) 查看數據表（PDF） - Maxim Integrated
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MAX4760 Datasheet PDF : 14 Pages
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High-Bandwidth, Quad DPDT Switches
Timing Circuits/Timing Diagrams (continued)
TxD+
A
B
INPUT A
Rs
CL
INPUT A-
A-
TxD-
Rs
Rs = 39Ω
CL = 50pF
B-
CL
OUTPUT B
OUTPUT B-
|tro - tri| DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
|tfo - tfi| DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
|tskew_o| CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
|tskew_i| CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
Figure 4. Input/Output Skew Timing Diagram
tri
90%
50%
10%
tskew_i
90%
50%
10%
tfi
tro
90%
50%
10%
tskew_o
90%
50%
10%
tfo
MAX4760
MAX4761
VGEN
RGEN NC_
OR NO_
GND
V+
V+
COM_
IN_
VIL TO VIH
VOUT
CL
VOUT
IN
OFF
ΔVOUT
OFF
ON
ON
OFF
OFF
IN
Q = (ΔVOUT)(CL)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 5. Charge Injection
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