V360EPC 查看數據表（PDF） - QuickLogic Corporation

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V360EPC

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V360EPC Rev. A0 / A1

LOCAL BUS TO PCI BRIDGE

FOR DE-MULTIPLEXED A/D PROCESSORS

• Glueless interface to i960Cx/Hx and

AMD29030/40 processors

• Configurable for primary master, bus master or

target operation.

• Type 0 and type 1 configuration cycles.

• Up to 1Kbyte burst access on PCI or local.

• Large, 640-byte FIFOs using V3’s unique

DYNAMIC BANDWIDTH ALLOCATION™ architecture

• 64-byte read FIFO per aperture.

• Enhanced support for 8/16-bit local bus devices

with programmable region sizes.

• 3.3 volt support

• Dual bi-directional address space remapping

• Fully compliant with PCI 2.1 specification

• On-the-fly byte order (endian) conversion

• I2O ATU and messaging unit including

hardware controlled circular queues

• 2 channel DMA controller plus multiprocessor

DMA chaining and demand mode DMA

• Hot swapping capability

• 16 8-bit bi-directional mailbox registers with

doorbell interrupts

• Flexible PCI and local interrupt management

• Optional power-on serial EEPROM initialization

• 33MHz and 50MHz local bus versions

• Industrials Temperature Grade -40 to +85’C

• Low cost 160-pin EIAJ PQFP package

V360EPC provides the highest performance,

most flexible, and most economical method to

directly connect i960Cx/Hx or AMD2930/40

processors to the PCI bus. As a generic solution

for 32-bit de-multiplexed local bus applications,

V360EPC is also a suitable candidate for a

variety of high-performance applications based

on Motorola, IBM, DEC and Hitachi embedded

processors - where a minimal amount of glue

logic is needed.

V360EPC is the second generation of V3’s I2O

ready PCI bridges - fully backward compatible

with V962PBC and V292PBC Rev B2 devices -

and is supporting powerful features like Hot

Swap and DMA chaining. The PCI bus can be

run at full 33MHz, independent of local bus clock

rate. The overall throughput of the system is

dramatically improved by increasing the FIFO

depths and utilizing the unique DYNAMIC

BANDWIDTH ALLOCATION™ architecture.

Access to the PCI bus can be performed through

two programmable address apertures. Two more

apertures are provided for PCI-to-local bus

accesses. There are 64-bytes of read FIFOs in

each direction, 32-bytes dedicated for each

aperture.

Two high-performance DMA channels with

chaining and demand mode capabilities provide

a powerful data transfer engine for bulk data

transfers. Mailbox registers and flexible PCI

interrupt controllers are also included to provide

a simple mechanism to emulate PCI device

control ports. The part is available in 160-pin low

cost PQFP packages.

i960Cx/Hx

CPU

V 96BMC

D

MEMORY

R

CONTROL

A

M

ROM

TYPICAL APPLICATION

V360EPC

LOCAL TO

PCI BRIDGE

PCI

PERIPHERAL

PCI SLOT or EDGE CONNECTOR

Copyright © 1998, V3 Semiconductor Corp.

V360EPC Data Sheet Rev 1.2

1

V3 Semiconductor reserves the right to change the specifications of this product without notice.

V360EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.

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