V360EPC 查看數據表（PDF） - QuickLogic Corporation

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V360EPC

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V360EPC

Table 3: Signal Descriptions (cont’d)

Configuration

Signal

Type

R Description

RDIR

I

Reset direction. Tie low to drive PRST out and LRST in, high to

drive LRST out and PRST in.

EN5V

I

Selects 5V (EN5V driven low) or 3.3V (EN5V driven high) device

operation modes.

Power and Ground Signals

Signal

Type

R Description

VCC

-

POWER leads intended for external connection to a VCC board

plane.

GND

-

GROUND leads intended for external connection to a GND board

plane.

a. R indicates state during reset.

b. Applies to AMD29030/40 mode.

c. Applies to i960Cx/Hx mode.

2.1 Test Mode Pins

Several device pins are used during manufacturing test to put the V360EPC device into various test

modes. These pins must be maintained at proper levels during reset to insure proper operation.

This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if

they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for

test mode pins:

Table 4: RESET State for Test Mode Pins

Mode

i960Cx/Hx

AMD2930/40

Pin 134

Pull-Up

Pull-Down

Pin 135

Pull-Up

Pull-Up

Pin 153

Pull-Up

Pull-Up

Copyright © 1998, V3 Semiconductor Corp.

V360EPC Data Sheet Rev 1.2

5

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