V360EPC 查看數據表（PDF） - QuickLogic Corporation

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V360EPC

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V360EPC

Table 5: Pin Assignments (cont’d)

PIN #

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

Signal

AD20

AD19

AD18

AD17

AD16

C/BE2

FRAME

GND

IRDY

TRDY

DEVSEL

STOP

PERR

SERR

PAR

C/BE1

AD15

GND

PIN #

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

Signal

LA31

LD1/ID1

LA30

LD2/ID2

LA29

LD3/ID3

LA28

LD4/ID4

LA27

LD5/ID5

LA26

LD6/ID6

LA25

LD7/ID7

LA24

LPAR0

LPAR1

GND

PIN # Signal PIN #

103 LD17/ID17 143

104

LA13

144

105 LD18/ID18 145

106

LA12

146

107 LD19/ID19 147

108

LA11

148

109 LD20/ID20 149

110

LA10

150

111 LD21/ID21 151

112

LA9

152

113 LD22/ID22 153

114

LA8

154

115 LD23/ID23 155

116

LA7

156

117

LPAR2

157

118

LPAR3

158

119 LD24/ID24 159

120

GND

160

Signal

EN5V

VCC

BE3

BWE3a

BE2

BWE2a

BE1

BWE1a

BE0

BWE0a

BLAST

BURSTa

W/R

R/Wa

RDIR

LRST

’1’

LINT

SDA

SCL/

LPERR

INTA

INTB

INTC

GND

a. Applies to AMD29030/40 mode.

Copyright © 1998, V3 Semiconductor Corp.

V360EPC Data Sheet Rev 1.2

7

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