V292PBC-40REVB2 查看數據表（PDF） - QuickLogic Corporation

零件编号

产品描述 (功能)

生产厂家

V292PBC-40REVB2

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V292PBC

Signal

ID[31:0]

LA[31:2]

BWE[3:0]

R/W

LREQ

RDY

LBREQ

LBGRT

LPAR[3:0]

BURST

ERR

LINT

LRST

MEMCLK

Table 3: Signal Descriptions (cont’d)

Type

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

O4

I

I/O4

I/O4

I/O4

O4

I/O4

I

Local Bus Interface

R

Description

Z Local instruction and data bus.

Z Local address bus.

Z Local bus byte write enablesb.

Z Read/Write.

Z Asserted low to indicate the beginning of a bus cycle.

Z Local Bus data ready.

L

Local bus request: asserted by the chip to initiate a local bus mas-

ter cycle.

Local bus grant.

Z Local bus parity.

Z Burst request.

Z Bus Time-out error.

H Local interrupt request.

L/Z Local bus RESET signal.

Local bus clock.

Signal

SCL/LPERR

SDA

Type

O4

I/O4

Serial EEPROM Interface

R

Description

X EEPROM clock. Local parity error.

X EEPROM data.

Signal

RDIR

Type

I

Configuration

R

Description

Reset direction. Tie low to drive PRST out and LRST in, high to

drive LRST out and PRST in.

4

V292PBC Data Sheet Rev 2.4

Copyright © 1998, V3 Semiconductor Inc.

Share Link: