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TC4468CPD

LOGIC-INPUT CMOS QUAD DRIVERS

TelCom Semiconductor Inc => Microchip 

LOGIC-INPUT CMOS

QUAD DRIVERS

1

TC4467

TC4468

TC4469

ELECTRICAL CHARACTERISTICS: Measured throughout operating temperature range with 4.5V ≤ VDD ≤ 18V,

Symbol

Parameter

unless otherwise specified.

Test Conditions

Min

Typ Max

2 Unit

Input

VIH

VIL

IIN

Output

VOH

VOL

RO

IPK

I

Logic 1, High Input Voltage

Logic 0, Low Input Voltage

Input Current

High Output Voltage

Low Output Voltage

Output Resistance

Peak Output Current

Latch-Up Protection

Withstand Reverse Current

(Note 3)

(Note 3)

0V ≤ VIN ≤ VDD

ILOAD = 100 µA (Note 1)

ILOAD = 10 mA (Note 1)

IOUT = 10 mA, VDD = 18V

4.5V ≤ VDD ≤ 16V

2.4

—

—

V

—

—

0.8

V

– 10

—

10

µA

VDD – 0.025 —

—

V

—

—

0.30

V

3

—

20

30

Ω

—

1.2

—

A

500

—

—

mA

Switching Time

tR

Rise Time

tF

Fall Time

tD1

Delay Time

tD2

Delay Time

Power Supply

Figure 1

Figure 1

Figure 1

Figure 1

—

—

—

—

50

50

nsec

nsec

4

—

—

100

nsec

—

—

100

nsec

IS

Power Supply Current

IS

Power Supply Voltage

Note 2

—

—

8

mA

4.5

—

18

V

NOTES: 1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to

drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.

2. When driving all four outputs simultaneously in the same direction, VDD shall be limited to 16V. This reduces the chance that internal

dv/dt will cause high-power dissipation in the device.

3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to

dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5 µs to avoid high internal

peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input

levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.

5

PIN CONFIGURATIONS

16-Pin SOIC (Wide)

6

14-Pin Plastic DIP/CerDIP

1A

1B

2A

2B

3A

3B

GND

GND

1

16

VDD

2

15

VDD

3

14 1Y

4

13 2Y

5 TC4467/8/9 12 3Y

6

11 4Y

7

10 4B

8

9

4A

1A 1

14 VDD

1B 2

13 1Y

2A 3

12 2Y

7

2B 4 TC4467/8/9 11 3Y

3A 5

10 4Y

3B 6

9 4B

GND 7

8 4A

8

TELCOM SEMICONDUCTOR, INC.

4-263

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