74HCT652D,118 查看數據表（PDF） - NXP Semiconductors.
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74HCT652D,118 Datasheet PDF : 10 Pages
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Philips Semiconductors
Octal bus transceiver/register; 3-state
Product specification
74HC/HCT652
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI.
Note to the HCT types
The value of additional quiescent supply current (∆ICC) for unit a load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below
INPUT
UNIT LOAD COEFFICIENT
SAB, SBA
A0 to A7 and B0 to B7
CPAB, CPBA
OEAB
OEBA
0.75
0.75
1.50
1.50
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITIONS
INPUT PARAMETER
MIN.
+25
TYP.
MAX.
−40 to +85
MIN. MAX.
−40 to +125
MIN. MAX.
UNIT
VCC
(V)
WAVEFORMS
tPHL/tPLH propagation delay
−
An, Bn to Bn, An
tPHL/tPLH propagation delay
−
CPAB, CPBA to Bn, An
tPHL/tPLH propagation delay
−
SAB, SBA to Bn, An
tPZH/tPZL 3-state output enable
−
time
OEAB, OEBA to An, Bn
tPHZ/tPLZ 3-state output disable −
time
OEAB, OEBA to An, Bn
tTHL/tTLH output transition time
−
16 27 − 34 −
23 39 − 49 −
27 46 − 55 −
18 33 − 41 −
16 35 − 44 −
5 12 − 15 −
41 ns 4.5 Fig.6
59 ns 4.5 Fig.7
66 ns 4.5 Fig.8
50 ns 4.5 Fig.9
53 ns 4.5 Fig.9
18 ns 4.5 Fig.6, 8
tW
clock pulse width
16 6 −
20 −
24 −
ns 4.5 Fig.7
HIGH or LOW
CPAB or CPBA
tsu
set-up time
10 5 −
13 −
15 −
ns 4.5 Fig.7
An, Bn to CPAB, CPBA
th
hold time
5 −2 −
6−
8
−
ns 4.5 Fig.7
An, Bn to CPAB, CPBA
fmax
maximum clock pulse 30 83 −
24 −
20 −
MHz 4.5 Fig.7
frequency
September 1993
7
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