AP65200FK-7 查看數據表（PDF） - Diodes Incorporated.

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AP65200FK-7

LIGHT LOAD IMPROVED 2A SYNCH DC/DC BUCK CONVERTER

Diodes Incorporated. 

PART OBSOLETE

NO ALTERNATE PART

AP65200

Pin Descriptions

Pin Number

Pin

Name

SO-8

SO-8EP

MSOP-8EP

U-DFN2626-10

Function

BST

1

2

High-Side Gate Drive Boost Input. BST supplies the drive for the high-side N-Channel MOSFET a

0.01µF or greater capacitor from SW to BST to power the high side switch.

IN

2

Power Input. IN supplies the power to the IC, as well as the step-down converter switches. Drive

3

IN with a 4.7V to 18V power source. Bypass IN to GND with a suitably large capacitor to eliminate

noise on the input to the IC. See Input Capacitor.

SW

3

Power Switching Output. SW is the switching node that supplies power to the output. Connect the

4

output LC filter from SW to the output load. Note that a capacitor is required from SW to BST to

power the high-side switch.

GND

4

5. 6

Ground

FB

5

Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage

7

divider connected to it from the output voltage. The feedback threshold is 0.925V. See Setting the

Output Voltage.

COMP

6

Compensation Node. COMP is used to compensate the regulation control loop. Connect a series

8

RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is

required. See Compensation Components.

EN

7

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the

regulator; low to turn it off.

9

Attach EN to IN with a 100kΩ pull up resistor for automatic startup. With this configuration an

internal voltage clamp ensures that a safe voltage is set for Enable not to exceed the absolute

maximum voltage for this pin.

SS

8

Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to

10

set the soft-start period. A 0.1µF capacitor sets the soft-start period to 15ms. To disable the soft-

start feature, leave SS floating.

AGND

NA

1

Analog GND

PAD

-

-

Exposed PAD for thermal performance improvement connect to GND (Note 4)

Note: 4. PAD’s soldering area needs to be at least 80%.

Functional Block Diagram

FB 5

SS 8

COMP 6

EN 7

+

-

1.1V

+

-

0.3 V

-

+

+

0.923 V

OVP

OSCILLATOR

RAMP

E

100/340 KHz CLK

+

ERROR

AMPLIFIER

-

6uA

+

2.5V

-

+

-

0.9V

EN OK

LOCKOUT

COMPARATOR

SHUTDOWN

COMPARATOR

CURRENT

SENSE

AMPLIFIER

2 IN

Logic

CURRENT

COMPARATOR

1 BS

100mΩ

3 SW

100mΩ

4 GND

disable

IN < 4.10V

IN

INTERNAL

5V

REGULATORS

AP65200

Document number: DS35548 Rev. 9 - 4

2 of 18

www.diodes.com

February 2018

© Diodes Incorporated

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