AD9136-EBZ 查看數據表（PDF） - Analog Devices
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AD9136-EBZ Datasheet PDF : 117 Pages
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AD9135/AD9136
Data Sheet
SYSREF SIGNAL TO DAC CLOCK TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.
Table 5.
Parameter
SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns
Setup Time
Hold Time
SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns
Setup Time
Hold Time
SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns
Setup Time
Hold Time
Test Conditions/Comments
AC-coupled
DC-coupled
AC-coupled
DC-coupled
AC-coupled
DC-coupled
AC-coupled
DC-coupled
AC-coupled
DC-coupled
AC-coupled
DC-coupled
Min Typ
126
131
92
119
96
104
77
95
83
90
68
84
Max Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 6.
Parameter
LATENCY
Interface
Interpolation
1×
2×
4×
8×
Inverse Sinc
Digital Gain Adjust
POWER-UP TIME
Min
Typ
Max
Unit
17
PClock1 cycles
66
DAC clock cycles
137
DAC clock cycles
251
DAC clock cycles
484
DAC clock cycles
17
DAC clock cycles
12
DAC clock cycles
60
µs
1 PClock is the AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.
Rev. C | Page 8 of 117
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