ADIS16136AMLZ(RevD) 查看數據表（PDF） - Analog Devices
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ADIS16136AMLZ Datasheet PDF : 20 Pages
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ADIS16136
Data Sheet
TIMING SPECIFICATIONS
TA = 25°C, VDD = 5 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
t2
t3
tx
Description
Serial clock
Stall period between data, see Figure 3
Read rate
Chip select to clock edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise and fall times
DOUT rise and fall times
CS high after SCLK edge
Input sync positive pulse width
Input sync to data ready output
Input sync period
Input sync low time
1 Guaranteed by design and characterization but not tested in production.
Min 1
0.01
15
25
48.8
24.4
48.8
0
5
488
100
Normal Mode
Typ
Max
2.5
25
5
12.5
5
12.5
300
Timing Diagrams
CS
SCLK
tCS
1
DOUT
MSB
DIN
R/W
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
Figure 2. SPI Timing and Sequence
tREADRATE
tSTALL
CS
SCLK
SYNC
CLOCK (CLKIN)
DATA
READY
Figure 3. Stall Time and Data Rate
t3
t2
t1
tX
Figure 4. Input Clock Timing Diagram
Unit
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
Rev. D | Page 4 of 20
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