DS2482S-800(2009) 查看數據表（PDF） - Maxim Integrated

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DS2482S-800
(Rev.:2009)

Eight-Channel 1-Wire Master

Maxim Integrated 

DS2482-800: Eight-Channel 1-Wire Master

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

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Note 13:

Note 14:

Note 15:

Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at

400KHz in Overdrive.

With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the

passive pullup on threshold VIL1 may not be reached in the available time. With Overdrive speed the

capacitive load on the 1-Wire bus must not exceed 300pF.

Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN.

Active or resistive pullup choice is configurable.

Fall time high to low (tF1) is derived from PDSRC, referenced from 0.9 × VCC to 0.1 × VCC.

These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For

reduced load, the pulldown slew rate is slightly faster.

All I²C timing values are referred to VIHmin and VILmax levels.

Applies to SDA, SCL, and AD0, AD1, AD2.

I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off.

The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement

tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the LOW

period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the

standard-mode I²C-bus specification) before the SCL line is released.

CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according

to I²C-Bus Specification v2.1 are allowed.

I²C communication should not take place for the max tOSCWUP time following a power-on reset.

Except for tF1, all 1-Wire timing specifications and tAPUOT are derived from the same timing circuit.

Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of

these parameters deviate from their typical value in the same direction and by the same degree.

PIN DESCRIPTION

PIN

NAME

FUNCTION

1

IO3

IO Driver for 1-Wire Line #3

2

SCL

I²C Serial Clock Input; must be tied to VCC through a pullup resistor.

3

SDA

I²C Serial Data Input/Output; must be tied to VCC through a pullup resistor.

4

VCC

Power Supply Input

5

NC

Not Connected

6

7

8

AD2

AD1

AD0

I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave

address of the device, see Figure 8.

9

IO7

IO Driver for 1-Wire Line #7

10

IO6

IO Driver for 1-Wire Line #6

11

IO5

IO Driver for 1-Wire Line #5

12

IO4

IO Driver for 1-Wire Line #4

13

GND

Ground Reference

14

IO0

IO Driver for 1-Wire Line #0

15

IO1

IO Driver for 1-Wire Line #1

16

IO2

IO Driver for 1-Wire Line #2

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