DS2482-100(2009) 查看數據表（PDF） - Maxim Integrated

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DS2482-100
(Rev.:2009)

Single-Channel 1-Wire Master

Maxim Integrated 

Single-Channel 1-Wire Master

1-Wire Single Bit

Command Code

Command Parameter

87h

Bit Byte

Description

Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the 1-Wire

line (see Table 2). A V value of 0b generates a write-zero time slot (Figure 5); a V value of 1b

generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In either

case, the logic level at the 1-Wire line is tested at tMSR and SBR is updated.

Typical Use

Restriction

Error Response

Command Duration

1-Wire Activity

Read Pointer Position

Status Bits Affected

Configuration Bits Affected

To perform single-bit writes or reads at the 1-Wire line when single bit communication is

necessary (the exception).

1-Wire activity must have ended before the DS2482-100 can process this command.

Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is

received and the command is ignored.

tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit byte.

Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.

Status Register (for busy polling and data reading).

1WB (set to 1 for tSLOT), SBR is updated at tMSR, DIR (may change its state).

1WS, APU, SPU apply.

Table 2. Bit Allocation in the Bit Byte

BIT 7

V

x = Don’t care.

BIT 6

x

BIT 5

x

BIT 4

x

BIT 3

x

BIT 2

x

BIT 1

x

BIT 0

x

VCC

VIH1

VIL1

0V

tF1

RESET PULSE

PRESENCE/SHORT DETECT

PRESENCE PULSE

tSI

tMSP

APU CONTROLLED

EDGE

tRSTL

PULLUP

RESISTIVE PULLUP

tRSTH

DS2482-100 PULLDOWN

1-Wire SLAVE PULLDOWN

Figure 4. 1-Wire Reset/Presence-Detect Cycle

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