GTLP6C817MTC 查看數據表（PDF） - Fairchild Semiconductor

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GTLP6C817MTC

Low Drive GTLP-to-LVTTL 1:6 Clock Driver

Fairchild Semiconductor 

Test Circuit and Timing Waveforms

Test Circuit for A Outputs

Test Circuit for B Outputs

Note A: CL includes probes and jig capacitance.

Voltage Waveform - Propagation Delay Times

Note A: CL includes probes and jig capacitance.

Note B: For B Port CL = 30 pF is used for worst case.

Voltage Waveform - Enable and Disable Times

Output Waveform 1 is for an output with internal conditions such that the

output is LOW except when disabled by the control output

Output Waveforms 2 is for an output with internal conditions such that the

output is HIGH except when disabled by the control output

Input and Measure Conditions

A or LVTTL

Pins

B or GTLP

Pins

VinHIGH

VCC

1.5

VinLOW

0.0

0.0

VM

VCC/2

1.0

VX

VOL + 0.3V

N/A

VY

VOH + 0.3V

N/A

All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns, ZO = 50Ω.

The outputs are measured one at a time with one transition per measurement.

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