MCF5272CVF66 查看數據表（PDF） - Freescale Semiconductor
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MCF5272CVF66 Datasheet PDF : 544 Pages
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List of Figures (Continued)
Figure
Number
Title
Page
Number
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
20-23
20-24
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
22-1
22-2
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination ................................................. 20-9
Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination................ 20-9
Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination .............. 20-10
Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................ 20-10
Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination ................ 20-11
Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ................ 20-11
Longword Read; EBI=11; 32-Bit Port; Internal Termination................................................ 20-12
Word Write; EBI=11; 16/32-Bit Port; Internal Termination .................................................. 20-13
Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination................................. 20-14
Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination ................ 20-14
Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination................................... 20-15
Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination .................. 20-15
Longword Read with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-16
Longword Write with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-17
Example of a Misaligned Longword Transfer...................................................................... 20-18
Example of a Misaligned Word Transfer ............................................................................. 20-18
Longword Write Access To 32-Bit Port Terminated with TEA Timing................................. 20-20
Master Reset Timing ........................................................................................................... 20-22
Normal Reset Timing .......................................................................................................... 20-23
Software Watchdog Timer Reset Timing ............................................................................ 20-24
Soft Reset Timing ............................................................................................................... 20-25
Test Access Port Block Diagram........................................................................................... 21-2
TAP Controller State Machine............................................................................................... 21-3
Output Cell (O.Cell) (BC–1) .................................................................................................. 21-4
Input Cell (I.Cell). Observe only (BC–4)................................................................................ 21-5
Output Control Cell (En.Cell) (BC–4) .................................................................................... 21-5
Bidirectional Cell (IO.Cell) (BC–6)......................................................................................... 21-6
General Arrangement for Bidirectional Pins.......................................................................... 21-6
Bypass Register .................................................................................................................... 21-8
MCF5272 Pinout (196 MAPBGA) ......................................................................................... 22-1
196 MAPBGA Package Dimensions (Case No. 1128A-01) .................................................. 22-2
Clock Input Timing Diagram.................................................................................................. 23-5
General Input Timing Requirements ..................................................................................... 23-7
Read/Write SRAM Bus Timing.............................................................................................. 23-9
SRAM Bus Cycle Terminated by TA ................................................................................... 23-10
SRAM Bus Cycle Terminated by TEA................................................................................. 23-11
Reset and Mode Select/HIZ Configuration Timing.............................................................. 23-12
Real-Time Trace AC Timing................................................................................................ 23-13
BDM Serial Port AC Timing................................................................................................. 23-13
SDRAM Signal Timing ........................................................................................................ 23-15
SDRAM Self-Refresh Cycle Timing .................................................................................... 23-16
MII Receive Signal Timing Diagram.................................................................................... 23-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
xi
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