MCF5272CVF66 查看數據表（PDF） - Freescale Semiconductor

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MCF5272CVF66

ColdFire® Integrated Microprocessor

Freescale Semiconductor 

List of Figures

Figure

Number

Title

Page

Number

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

3-1

3-2

4-1

4-2

4-3

4-4

4-5

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

5-21

5-22

MCF5272 Block Diagram ........................................................................................................ 1-2

ColdFire Pipeline..................................................................................................................... 2-2

ColdFire Multiply-Accumulate Functionality Diagram.............................................................. 2-3

ColdFire Programming Model ................................................................................................. 2-5

Condition Code Register (CCR).............................................................................................. 2-6

Status Register (SR) ............................................................................................................... 2-8

Vector Base Register (VBR) ................................................................................................... 2-8

Organization of Integer Data Formats in Data Registers ...................................................... 2-10

Organization of Integer Data Formats in Address Registers................................................. 2-10

Memory Operand Addressing ............................................................................................... 2-11

Exception Stack Frame Form................................................................................................ 2-27

ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1

MAC Programming Model....................................................................................................... 3-2

SRAM Base Address Register (RAMBAR) ............................................................................. 4-3

ROM Base Address Register (ROMBAR).............................................................................. 4-5

Instruction Cache Block Diagram............................................................................................ 4-8

Cache Control Register (CACR) ........................................................................................... 4-12

Access Control Register Format (ACRn) .............................................................................. 4-14

Processor/Debug Module Interface......................................................................................... 5-1

PSTCLK Timing ...................................................................................................................... 5-2

Example JMP Instruction Output on PST/DDATA .................................................................. 5-5

Debug Programming Model .................................................................................................... 5-6

Address Attribute Trigger Register (AATR)............................................................................. 5-7

Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9

Configuration/Status Register (CSR) .................................................................................... 5-10

Data Breakpoint/Mask Registers (DBR and DBMR) ............................................................. 5-12

Program Counter Breakpoint Register (PBR) ....................................................................... 5-13

Program Counter Breakpoint Mask Register (PBMR)........................................................... 5-13

Trigger Definition Register (TDR).......................................................................................... 5-14

BDM Serial Interface Timing ................................................................................................. 5-17

Receive BDM Packet ............................................................................................................ 5-18

Transmit BDM Packet ........................................................................................................... 5-18

BDM Command Format ........................................................................................................ 5-20

Command Sequence Diagram.............................................................................................. 5-21

RAREG/RDREG Command Format .......................................................................................... 5-22

RAREG/RDREG Command Sequence...................................................................................... 5-22

WAREG/WDREG Command Format ......................................................................................... 5-23

WAREG/WDREG Command Sequence .................................................................................... 5-23

READ Command/Result Formats ........................................................................................... 5-24

READ Command Sequence ................................................................................................... 5-24

MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3

Freescale Semiconductor

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