MCF5272CVM66 查看數據表（PDF） - Freescale Semiconductor

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MCF5272CVM66

ColdFire® Integrated Microprocessor

Freescale Semiconductor 

List of Figures (Continued)

Figure

Number

Title

Page

Number

11-28

12-1

12-2

12-3

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12-6

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12-12

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13-1

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Transmit Buffer Descriptor (TxBD)..................................................................................... 11-37

The USB “Tiered Star” Topology........................................................................................... 12-2

USB Module Block Diagram.................................................................................................. 12-3

USB Frame Number Register (FNR) .................................................................................... 12-9

USB Frame Number Match Register (FNMR)....................................................................... 12-9

USB Real-Time Frame Monitor Register (RFMR)............................................................... 12-10

USB Real-Time Frame Monitor Match Register (RFMMR)................................................. 12-11

USB Function Address Register (FAR)............................................................................... 12-11

USB Alternate Settings Register (ASR) .............................................................................. 12-12

USB Device Request Data 1 Register (DRR1) ................................................................... 12-13

USB Device Request Data 2 Register (DRR2) ................................................................... 12-13

USB Specification Number Register (SPECR) ................................................................... 12-14

USB Endpoint 0 Status Register (EP0SR).......................................................................... 12-14

USB Endpoint 0 IN Configuration Register (IEP0CFG) ...................................................... 12-15

USB Endpoint 0 OUT Configuration Register ..................................................................... 12-16

USB Endpoint 1–7 Configuration Register.......................................................................... 12-16

USB Endpoint 0 Control Register (EP0CTL)....................................................................... 12-17

USB Endpoint 1-7 Control Register (EPnCTL) ................................................................... 12-20

USB Endpoint 0 Interrupt Mask (EP0IMR)

and General/Endpoint 0 Interrupt Registers (EP0ISR) ....................................................... 12-22

USB Endpoints 1–7 Interrupt Status Registers (EPnISR)................................................... 12-25

USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) ...................................................... 12-26

USB Endpoint 0-7 Data Registers (EPnDR) ....................................................................... 12-27

USB Endpoint 0-7 Data Present Registers (EPnDPR) ....................................................... 12-28

Example USB Configuration Descriptor Structure .............................................................. 12-29

Recommended USB Line Interface..................................................................................... 12-36

USB Protection Circuit ........................................................................................................ 12-37

PLIC System Diagram........................................................................................................... 13-2

GCI/IDL Receive Data Flow .................................................................................................. 13-3

GCI/IDL B-Channel Receive Data Register Demultiplexing.................................................. 13-4

GCI/IDL Transmit Data Flow ................................................................................................. 13-4

GCI/IDL B Data Transmit Register Multiplexing.................................................................... 13-5

B-Channel Unencoded and HDLC Encoded Data ................................................................ 13-6

D-Channel HDLC Encoded and Unencoded Data. ............................................................... 13-7

D-Channel Contention .......................................................................................................... 13-8

GCI/IDL Loopback Mode ...................................................................................................... 13-9

Periodic Frame Interrupt ..................................................................................................... 13-10

PLIC Internal Timing Signal Routing ................................................................................... 13-12

PLIC Clock Generator ......................................................................................................... 13-12

B1 Receive Data Registers P0B1RR–P3B1RR .................................................................. 13-15

B2 Receive Data Registers P0B2RR – P3B2RR ................................................................ 13-16

D Receive Data Registers P0DRR–P3DRR ....................................................................... 13-16

B1 Transmit Data Registers P0B1TR–P3B1TR.................................................................. 13-17

B2 Transmit Data Registers P0B2TR–P3B2TR.................................................................. 13-17

MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3

viii

Freescale Semiconductor

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