MCF5272CVF66 查看數據表（PDF） - Freescale Semiconductor

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MCF5272CVF66

ColdFire® Integrated Microprocessor

Freescale Semiconductor 

List of Figures (Continued)

Figure

Number

Title

Page

Number

13-18

13-19

13-20

13-21

13-22

13-23

13-24

13-25

13-26

13-27

13-28

13-29

13-30

13-31

13-32

13-33

13-34

13-35

13-36

13-37

13-38

13-39

13-40

13-41

13-42

14-1

14-2

14-3

14-4

14-5

14-6

14-7

14-8

14-9

14-10

14-11

15-1

15-2

15-3

15-4

15-5

15-6

16-1

16-2

D Transmit Data Registers P0DTR–P3DTR ....................................................................... 13-18

Port Configuration Registers (P0CR–P3CR) ...................................................................... 13-18

Loopback Control Register (PLCR)..................................................................................... 13-20

Interrupt Configuration Registers (P0ICR–P3ICR).............................................................. 13-20

Periodic Status Registers (P0PSR–P3PSR)....................................................................... 13-22

Aperiodic Status Register (PASR) ...................................................................................... 13-23

GCI Monitor Channel Receive Registers (P0GMR–P3GMR) ............................................. 13-24

GCI Monitor Channel Transmit Registers (P0GMT–P3GMT) ............................................. 13-25

GCI Monitor Channel Transmit Abort Register (PGMTA) ................................................... 13-26

GCI Monitor Channel Transmit Status Register (PGMTS).................................................. 13-27

GCI C/I Channel Receive Registers (P0GCIR–P3GCIR) ................................................... 13-28

GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT) ................................................... 13-29

GCI C/I Channel Transmit Status Register (PGCITSR)...................................................... 13-30

D-Channel Status Register (PDCSR) ................................................................................. 13-31

D-Channel Request Registers (PDRQR) ............................................................................ 13-32

Sync Delay Registers (P0SDR–P3SDR) ............................................................................ 13-33

Clock Select Register (PCSR) ............................................................................................ 13-34

Port 1 Configuration Register (P1CR)................................................................................. 13-36

Port 1 Interrupt Configuration Register (P1ICR) ................................................................. 13-37

ISDN SOHO PABX Example .............................................................................................. 13-38

Standard IDL2 10-Bit Mode ................................................................................................ 13-39

ISDN SOHO PABX Example .............................................................................................. 13-40

Standard IDL2 10-Bit Mode ................................................................................................ 13-41

Two-Line Remote Access ................................................................................................... 13-41

Standard IDL2 8-Bit Mode .................................................................................................. 13-42

QSPI Block Diagram ............................................................................................................. 14-2

QSPI RAM Model.................................................................................................................. 14-5

QSPI Mode Register (QMR) ................................................................................................. 14-9

QSPI Clocking and Data Transfer Example........................................................................ 14-10

SPI Modes Timing............................................................................................................... 14-11

QSPI Delay Register (QDLYR) ........................................................................................... 14-11

QSPI Wrap Register (QWR) ............................................................................................... 14-12

QSPI Interrupt Register (QIR) ............................................................................................. 14-13

QSPI Address Register ....................................................................................................... 14-14

QSPI Data Register ............................................................................................................ 14-14

Command RAM Registers (QCR0–QCR15) ....................................................................... 14-15

Timer Block Diagram............................................................................................................. 15-2

Timer Mode Registers (TMR0–TMR3).................................................................................. 15-3

Timer Reference Registers (TRR0–TRR3) ........................................................................... 15-4

Timer Capture Registers (TCAP0–TCAP3) .......................................................................... 15-4

Timer Counter (TCN0–TCN3) ............................................................................................... 15-4

Timer Event Registers (TER0–TER3)................................................................................... 15-5

Simplified Block Diagram ...................................................................................................... 16-1

UART Mode Registers 1 (UMR1n)........................................................................................ 16-4

MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3

Freescale Semiconductor

ix

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