MC33932VW(2009) 查看數據表（PDF） - Freescale Semiconductor
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MC33932VW Datasheet PDF : 21 Pages
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ VPWR ≤ 28 V, -40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency(20)
Maximum Switching Frequency During Current Limit Regulation(21)
Output ON Delay(22)
VPWR = 14 V
Output OFF Delay(22)
VPWR = 14 V
ILIM Output Constant-OFF Time(23)
ILIM Blanking Time(24)
Disable Delay Time(25)
Output Rise and Fall Time(26)
Short-circuit / Over-temperature Turn-OFF (Latch-OFF) Time(27), (28)
Power-ON Delay Time(28)
Output MOSFET Body Diode Reverse Recovery Time(28)
Charge Pump Operating Frequency(28)
f PWM
–
f MAX
–
t DON
–
–
11
kHz
–
20
kHz
μs
–
18
t DOFF
–
μs
–
12
tA
15
20.5
32
μs
tB
12
16.5
27
μs
t DDISABLE
–
–
8.0
μs
t F, t R
1.5
3.0
8.0
μs
t FAULT
–
–
8.0
μs
t POD
–
1.0
5.0
ms
tRR
75
100
150
ns
fCP
–
7.0
–
MHz
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22. * Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See Figure 4, page 9.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
25. * Disable Delay Time measurement is defined in Figure 5, page 9.
26. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with VPWR = 14 V, RLOAD
= 3.0 ohm. See Figure 6, page 9.
27. Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents
possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short-circuit event detection and
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to “fold back”,
or decrease, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
28. Parameter is Guaranteed By Design.
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8
Analog Integrated Circuit Device Data
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