HEF4521B(2009) 查看數據表（PDF） - NXP Semiconductors.

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HEF4521B
(Rev.:2009)

24-stage frequency divider and oscillator

NXP Semiconductors. 

NXP Semiconductors

HEF4521B

24-stage frequency divider and oscillator

8. Functional Test

A test function has been included to reduce the test time required to test all 24 counter

stages. This test function divides the counter into three 8-stage sections by connecting

VSS1 to VDD and VDD1 to VSS. 255 counts are loaded into each of the 8-stage sections in

parallel via A2 (connected to Y2). All flip-flops are now at a HIGH level. The counter is now

returned to the normal 24-stage in series configuration by connecting VSS1 to VSS and

VDD1 to VDD. Entering one more pulse into input A2 will cause the counter to ripple from

an all HIGH state to an all LOW state.

Table 4. Functional test sequence

Inputs

Control terminals

MR A2

Y2

VSS1 VDD1

H

L

L

VDD VSS

L

see

see

VDD VSS

Remarks Remarks

column column

L

L

L

VSS VSS

L

H

L

VSS VSS

L

H

L

VSS VDD

L

↓

VSS VDD

Outputs Remarks

Q18 to Q24

L

counter is in three 8-stage sections in parallel mode; A2 and Y2

are interconnected (Y2 is now input); counter is reset by MR.

H

255 pulses are clocked into A2, Y2. The counter advances on

the LOW to HIGH transition.

H

VSS1 is connected to VSS.

H

the input A2 is made HIGH.

H

VDD1 is connected to VDD; Y2 is now made floating and

becomes an output; the device is now in the 224 mode.

L

counter ripples from an all HIGH state to an all LOW state.

[1] H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH to LOW transition.

9. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

VDD

IIK

VI

IOK

II/O

IDD

Tstg

Tamb

Ptot

supply voltage

input clamping current

input voltage

output clamping current

input/output current

supply current

storage temperature

ambient temperature

total power dissipation

VI < −0.5 V or VI > VDD + 0.5 V

VO < −0.5 V or VO > VDD + 0.5 V

to any supply terminal

DIP16 package

SO16 package

P

power dissipation

per output

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

Min

−0.5

-

−0.5

-

-

-

−65

−40

[1] -

[2] -

-

Max

Unit

+18

V

±10

mA

VDD + 0.5 V

±10

mA

±10

mA

±100

mA

+150

°C

+85

°C

750

mW

500

mW

100

mW

HEF4521B_5

Product data sheet

Rev. 05 — 5 November 2009

© NXP B.V. 2009. All rights reserved.

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