SN74LS322DW 查看數據表（PDF） - Motorola => Freescale
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SN74LS322DW Datasheet PDF : 4 Pages
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SN54 / 74LS322A
REGISTER
ENABLE
(1)
G
S/P (2)
SIGN
EXTEND
(18)
SE
(17)
DATA D1
SELECT
(19)
DS
D0
(3)
CLOCK (11)
CLEAR (9)
OUTPUT
ENABLE
(8)
OE
BLOCK DIAGRAM
Q
CK
DQ
CLR
Q
CK
DQ
CLR
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
Q
CK
DQ
CLR
Q
CK
DQ
CLR
(12)
QH
(4)
A/QA
(16)
B/QB
(7)
G/QG
(13)
H/QH
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
OPERATION
CLEAR
REGISTER
ENABLE
S/P
SIGN
EXTEND
DATA
SELECT
OUTPUT
ENABLE
CLOCK
A/QA B/QB C/QC … H/QH
OUTPUT
QH′
Clear
L
L
H
X
X
X
X
H
X
X
L
X
L
L
L
L
L
L
X
L
L
L
L
L
Hold
H
Shift Right
H
H
Sign Extend
H
Load
H
H
X
X
X
L
H
H
L
L
H
H
H
L
H
L
X
L
L
X
X
L
X
QA0 QB0 QC0 QH0
QH0
L
↑
D0 QAn QBn QGn
QGn
L
↑
D1 QAn QBn QGn
QGn
L
↑
QAn QAn QBn QGn
QGn
X
↑
a
b
c
h
h
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is
cleared while the eight input/output terminals are disabled to the high-impedance state.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW to HIGH level
QA0…QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established
QAn…QHn = the level of QA through QH, respectively, before the most recent ↑ transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a…h = the level of steady-state inputs at inputs A through H respectively
FAST AND LS TTL DATA
5-2
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