EP2S130F1020C3 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

EP2S130F1020C3

Stratix II Device Handbook, Volume 1

Unspecified 

Contents

Chapter Revision Dates .......................................................................... vii

About this Handbook ................................................................................ i

How to Contact Altera ............................................................................................................................... i

Typographic Conventions ......................................................................................................................... i

Section I. Stratix II Device Family Data Sheet

Revision History ....................................................................................................................... Section I–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–1

Document Revision History ................................................................................................................. 1–6

Chapter 2. Stratix II Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–4

LAB Control Signals ......................................................................................................................... 2–5

Adaptive Logic Modules ...................................................................................................................... 2–6

ALM Operating Modes ................................................................................................................... 2–9

Register Chain ................................................................................................................................. 2–20

Clear & Preset Logic Control ........................................................................................................ 2–22

MultiTrack Interconnect ..................................................................................................................... 2–22

TriMatrix Memory ............................................................................................................................... 2–28

Memory Block Size ......................................................................................................................... 2–29

Digital Signal Processing Block ......................................................................................................... 2–40

Modes of Operation ....................................................................................................................... 2–44

DSP Block Interface ........................................................................................................................ 2–44

PLLs & Clock Networks ..................................................................................................................... 2–48

Global & Hierarchical Clocking ................................................................................................... 2–48

Enhanced & Fast PLLs ................................................................................................................... 2–57

Enhanced PLLs ............................................................................................................................... 2–68

Fast PLLs .......................................................................................................................................... 2–69

I/O Structure ........................................................................................................................................ 2–69

Double Data Rate I/O Pins ........................................................................................................... 2–77

External RAM Interfacing ............................................................................................................. 2–81

Programmable Drive Strength ..................................................................................................... 2–83

Altera Corporation

iii

Share Link: