LFE3-35EA-8FN1156C 查看數據表（PDF） - Lattice Semiconductor

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LFE3-35EA-8FN1156C

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Figure 2-4. General Purpose PLL Diagram

FDA[3:0]

WRDEL

CLKI

CLKFB

CLKI

Divider

PFD

CLKFB

Divider

RSTK

RST

DRPAI[3:0]

DFPAI[3:0]

VCO/

Loop Filter

Architecture

LatticeECP3 Family Data Sheet

3

CLKOP

Divider

Phase/

Duty Cycle/

Duty Trim

Duty Trim

CLKOK

Divider

Lock

Detect

CLKOK2

CLKOS

CLKOP

CLKOK

LOCK

Table 2-4 provides a description of the signals in the PLL blocks.

Table 2-4. PLL Blocks Signal Descriptions

Signal

CLKI

CLKFB

RST

RSTK

WRDEL

CLKOS

CLKOP

CLKOK

CLKOK2

LOCK

FDA [3:0]

DRPAI[3:0]

DFPAI[3:0]

I/O

Description

I Clock input from external pin or routing

I PLL feedback input from CLKOP, CLKOS, or from a user clock (pin or logic)

I “1” to reset PLL counters, VCO, charge pumps and M-dividers

I “1” to reset K-divider

I DPA Fine Delay Adjust input

O PLL output to clock tree (phase shifted/duty cycle changed)

O PLL output to clock tree (no phase shift)

O PLL output to clock tree through secondary clock divider

O PLL output to clock tree (CLKOP divided by 3)

O “1” indicates PLL LOCK to CLKI

I Dynamic fine delay adjustment on CLKOS output

I Dynamic coarse phase shift, rising edge setting

I Dynamic coarse phase shift, falling edge setting

Delay Locked Loops (DLL)

In addition to PLLs, the LatticeECP3 family of devices has two DLLs per device.

CLKI is the input frequency (generated either from the pin or routing) for the DLL. CLKI feeds into the output muxes

block to bypass the DLL, directly to the DELAY CHAIN block and (directly or through divider circuit) to the reference

input of the Phase Detector (PD) input mux. The reference signal for the PD can also be generated from the Delay

Chain signals. The feedback input to the PD is generated from the CLKFB pin or from a tapped signal from the

Delay chain.

The PD produces a binary number proportional to the phase and frequency difference between the reference and

feedback signals. Based on these inputs, the ALU determines the correct digital control codes to send to the delay

2-7

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